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HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAMTM)
Integrated Device Technology, Inc.
IDT70824S/L
FEATURES:
* 4K x 16 Sequential Access Random Access Memory (SARAMTM) - Sequential Access from one port and standard Random Access from the other port - Separate upper-byte and lower-byte control of the Random Access Port * High speed operation - 20ns tAA for random access port - 20ns tCD for sequential port - 25ns clock cycle time * Architecture based on Dual-Port RAM cells * Electrostatic discharge > 2001V, Class II * Compatible with Intel BMIC and 82430 PCI Set * Width and Depth Expandable * Sequential side - Address based flags for buffer control - Pointer logic supports up to two internal buffers * Battery backup operation - 2V data retention * TTL-compatible, single 5V (+10%) power supply * Available in 80-pin TQFP and 84-pin PGA * Military product compliant to MIL-STD-883. * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications.
DESCRIPTION:
The IDT70824 is a high-speed 4K x 16-bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter sequencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 900mW of power at maximum high-speed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70824 is packaged in a 80-pin Thin Plastic Quad Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0-11
12
RST
SCLK Random Access Port Controls Sequential Access Port Controls
CE OE LB LSB UB MSB CMD
I/O0-15 R/W
4K X 16 Memory Array
16 12
CNTEN SOE SSTRT1 SSTRT2 SCE
SR/W
SLD
DataR AddrR RST
12 16 Reg. 12 16
DataL AddrL
12
SI/O0-15
12 12
Pointer/ Counter
Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status
12
EOB1
COMPARATOR
EOB2
3099 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3099/3
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IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (1,2)
INDEX SI/O1 SI/O0 GND N/C
SI/O2 SI/O3 VCC SI/O4 SI/O5 SI/O6 SI/O7 GND SI/O8 SI/O9 SI/O10 SI/O11 VCC SI/O12 SI/O13 SI/O14 SI/O15 GND N/C GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 2 58 3 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 56 55 54 53
SCE
RST
SR/W
SSTRT2 SSTRT1
SLD
IDT70824 PN80-1 TQFP TOP VIEW(3)
52 51 50 49 48 47 46 45 44 43 42
CNTEN
GND GND
SOE
SCLK GND
EOB2 EOB1
VCC I/O0
CMD CE
LB UB
R/W
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC VCC A1 A0
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
OE
I/O1 GND I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 VCC I/O12 I/O13 I/O14 I/O15 GND
63 61 60 58 55 54 48 46
3099 drw 02
I/O1
66
VCC
64
EOB1
62
51
45
42
GND CNTEN GND SSTRT2 SR/W NC
59 56
GND
43
NC
40
11 10 09 08 07 06 05 04 03 02 01
I/O2
67
NC
65
I/O0 EOB2
SOE
49
RST SLD SCE
52
50
47
44
SI/O0 SI/O1 SI/O3
41 39
57
53
I/O3 GND
69 68
SCLK GND SSTRT1
SI/O2 VCC
38 37
I/O4
72
VCC
71 73 33
SI/O4 SI/O5
35 34
I/O7
75
I/O6 GND
70 74
IDT70824 G84-3 84-PIN PGA TOP VIEW (3)
SI/O8 SI/O7 GND
32 31 36
I/O9
76
I/O5
77
I/O8
78
SI/O9 SI/O10 SI/O6
28 29 30
I/O10 I/O11 VCC
79 80
SI/O12 VCC SI/O11
26 27
I/O12 I/O13
81 83 7
SI/O14 SI/O13
I/O14
82 1
NC
2
CMD
A0
11
12
23
25
VCC
10
A2
14 17 20
NC SI/O15
22 24
I/O15 GND
84 3 4
OE
5
LB
8
VCC
15
A4
13
A7
16
A10
18
GND GND
19 21
NC A INDEX
R/W B
UB
C
6
CE
D
9
A1 E
A5 F
A3 G
A6 H
A8 J
A9 K
A11 L
3099 drw 03
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.30 2
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL A0-A11
CE
NAME Address Lines Chip Enable
I/O(1) I I I
DESCRIPTION Address inputs to access the 4096-word (16 bit) memory array. Random access data inputs/outputs for 16-bit wide data. When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMD may not be LOW at the same time. When CMD is LOW, Address lines A0-A2, R/W, and inputs/outputs I/O0-I/O11, are used to access the control register, the flag register, and the start and end of buffer registers. CMD and CE may not be LOW at the same time. If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the high-impedance state. When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0I/O7 are tri-stated and blocked during read and write operations. UB controls access for I/O8I/O15 in the same manner and is asynchronous from LB. Seven +5V power supply pins. All Vcc pins must be connected to the same +5V VCC supply. Ten Ground pins. All Ground pins must be connected to the same Ground supply.
3099 tbl 01
I/O0-I/O15 Inputs/Outputs
CMD
Control Register Enable Read/Write Enable
I
R/W
I
OE
Output Enable Lower Byte, Upper Byte Enables Power Supply Ground
I I
LB,UB
VCC GND
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL NAME SI/O0-15 Inputs SCLK Clock I/O(1) DESCRIPTION I/O Sequential data inputs/outputs for 16-bit wide data. I SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH transition of SCLK when CNTEN is LOW. Chip Enable I When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All data is retained, unless altered by the random access port. Counter Enable I When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is independant of SCE. Read/Write Enable I When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High transistion of SCLK if SR/W or SCE is High. Address Pointer I When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer Load Control changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. Load Start of I When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the Address Register address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. End of Buffer Flag O EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are dependent on separate internal registers, and therefore separate match addresses. Output Enable I SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers and the sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in the high-impedance state. SOE is asynchronous to SCLK. Reset I When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
3099 tbl 02
SCE
CNTEN
SR/W
SLD
SSTRT1, SSTRT2
EOB1, EOB2
SOE
RST
NOTE: 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
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IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Rating Commercial Military -0.5 to +7.0 Unit V Terminal Voltage -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current 0 to +70 -55 to +125 -55 to +125 50
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
3099 tbl 04
TA TBIAS TSTG IOUT
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. 5.5 0 6.0(2) 0.8 Unit V V V V
3099 tbl 05
NOTES: 3099 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25C, F = 1.0MHz)TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
NOTES: 3099 tbl 06 1. This parameter is determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V 10%)
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max. VIN = GND to VCC VCC = Max. CE and SCE = VIH VOUT = GND to VCC IOL = 4mA, VCC = Min. IOH = -4mA, VCC = Min. IDT70824S Min. Max. -- -- -- 2.4 5.0 5.0 0.4 -- IDT70824L Min. Max. -- -- -- 2.4 1.0 1.0 0.4 -- Unit A A V V
3099 tbl 07
NOTE: 1. At Vcc 2.0V input leakages are undefined.
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IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V 10%)
Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) ISB1 Standby Current (Both Ports - TTL Level Inputs) ISB2 Standby Current (One Port - TTL Level Input) ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) ISB4 Full Standby Current (One Port - CMOS Level Inputs) Test Condition
CE = VIL, Outputs Open, SCE = VIL(5)
Version MIL. S L
70824X20 70824X25 Com'l. Only Com'l. Only Typ.(2) Max. Typ.(2) Max. -- -- 180 180 -- -- 25 25 -- 115 115 -- -- 1.0 0.2 -- -- 110 110 -- -- 380 330 -- -- 70 50 -- ---- 260 230 -- -- 15 5 -- -- 240 200 -- -- 170 170 -- -- 25 25 -- -- 105 105 -- -- 1.0 0.2 -- -- 100 100 -- -- 360 310 -- -- 70 50 -- -- 250 220 -- -- 15 5 -- -- 230 190
70824X35
70824X45
Typ.(2) Max. Typ.(2) Max. Unit 160 160 160 160 20 20 20 20 95 95 95 95 1.0 0.2 1.0 0.2 90 90 90 90 400 340 340 290 85 65 70 50 290 250 240 210 30 10 15 5 260 215 220 180 155 155 155 155 16 16 16 16 90 90 90 90 1.0 0.2 1.0 0.2 85 85 85 85 400 mA 340 340 290 85 65 70 50 290 250 240 210 30 10 15 5 260 215 220 180 mA mA mA mA
f = fMAX(3)
SCE
and CE > VIH(7) MIL. CMD = VIH
COM'L. S L S L
f = fMAX(3)
CE
or SCE = VIH Active Port Outputs Open, f = fMAX(3)
COM'L. S L MIL. S L
COM'L. S L MIL. S L
Both Ports CE and (6) SCE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V, f = 0(4)
COM'L. S L S L
One Port CE or MIL. (6,7) SCE VCC - 0.2V Outputs Open
(Active port), f = fMAX(3) COM'L. S VIN VCC - 0.2V or VIN 0.2V L
NOTES: 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, Ta = +25C; guaranteed by device characterization but not production tested. 3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK. 6. SCE may be 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown. 7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High > Vcc - 0.2V and Low < 0.2V, and TTL High = VIH and Low = VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L VERSION ONLY) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol VDR ICCDR tCDR(3) tR
(3)
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
CE
Test Condition VCC = 2V = VHC MIL. COM'L. VIN = VHC or = VLC
SCE CMD
Min. 2.0 -- -- 0 tRC
(2)
Typ.(1) -- 100 100 -- --
Max. -- 4000 1500 -- --
Unit V A ns ns
3099 tbl 09
= VHC(4) when SCLK= > VHC
NOTES : 1. TA = +25C, VCC = 2V; guaranteed by device characterization but not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization, but is not production tested. 4. To initiate data retention, SCE = VIH must be clocked in.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT)(1, 2)
DATA RETENTION MODE VCC 4.5V tCDR VDR 2V 4.5V tR VDR VIH VIH
CE
SCLK
SCE
tPD ICC ISB NOTES : 1. SCE is synchronized to the sequential clock input. 2. CMD > VCC - 0.2V. ISB
3099 drw 04
tPU
5V 893 DATAOUT DATAOUT 347 30pF 347
5V 893
5pF
3099 drw 05
3099 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, tBHZ,tOHZ,tWHZ, tCKHZ, and tCKLZ) Including scope and jig.
8 7 6 tAA/tCD/tEB 5 (Typical, ns) 4 3 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load capacitance. 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
3099 drw 07
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1, 2, and 3
3099 tbl 10
2 1 -1 -2 -3
Figure 3. Lumped Capacitance Load Typical Derating Curve
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I - RANDOM ACCESS READ AND WRITE (1,2)
Inputs/Outputs MODE
CE
L L L L L L H L L H H
CMD
H H H H H H H H H L L
R/W W H H H L L L X H X L H
OE
L L L H(3) H
(3)
LB
L L H L L H X X H L(4) L(4)
UB
L H L L H L X X H L(4) L(4)
I/O0-I/O7 DATAOUT DATAOUT High-Z DATAIN DATAIN High-Z High-Z High-Z High-Z DATAIN DATAOUT
I/O8-I/O15 DATAOUT High-Z DATAOUT DATAIN High-Z DATAIN High-Z High-Z High-Z DATAIN DATAOUT Read both Bytes. Read lower Byte only. Read upper Byte only. Write to both Bytes. Write to lower Byte only. Write to upper Byte only. Both Bytes deselected and powered down. Outputs disabled but not powered down. Both Bytes deselected but not powered down. Write I/O0-I/O11 to the Buffer Command Register. Read contents of the Buffer Command Register via I/O0-I/O12.
H(3) X H X H(3) L
3099 tbl 11 NOTES: 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. 2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation. 3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven. 4. Byte operations to control register using UB and LB separately are also allowed.
TRUTH TABLE II - SEQUENTIAL READ (1,2,3,6,8)
Inputs/Outputs SCLK SCE L L L L L MODE SI/O [EOB1] [EOB2] Counter Advanced Sequential Read with EOB1 reached. Counter Advanced Sequential Read with EOB2 reached. [EOB1 - 1] Non-Counter Advanced Sequential Read, without EOB1 reached. [EOB2 - 1] Non-Counter Advanced Sequential Read without EOB2 reached. HIGH-Z Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached.
3099 tbl 12
CNTEN SR/W EOB1 EOB2 SOE W
L H L H L H H H H H LOW LAST LAST LAST LOW LAST LAST LOW LAST LOW L L L L H
TRUTH TABLE III - SEQUENTIAL WRITE (1,2,3,4,5,6,7,8)
Inputs/Outputs SCLK SCE CNTEN SR/W EOB1 EOB2 SOE W L L H H H L H L L L X X LAST LAST LOW LOW LAST LAST NEXT NEXT H H X X SI/O SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached SI/OIN Counter Advanced Sequential Write with EOB1 and EOB2 reached. High-Z No Write or Read due to Sequential port Deselect. No counter advance. High-Z No Write or Read due to Sequential port Deselect. Conter does advance. MODE
3099 tbl 13 NOTES: 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL. 2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations. 3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock during the cycle in which SR/W = VIL. 5. SI/OIN refers to SI/O0-SI/O15 inputs. 6. "LAST" refers to the previous value still being output, no change. 7. Termination of a write is done on the Low-to-High transition of SCLK if SR/W or SCE is High. 8. When CLKEN=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after Reset, Read (and write) Cycle".
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IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV - SEQUENTIAL ADDRESS POINTER OPERATIONS (1,2,3,4,5)
Inputs/Outputs SCLK
SSTRT1 SSTRT2 SLD SSTRT SSTRT SOE
H H L L H H H L H X X
MODE Start address for Buffer #1 loaded into Address Pointer. Start address for Buffer #2 loaded into Address Pointer.
H(6) Data on SI/O0-SI/O12 loaded into Address Pointer .
NOTES: 3099 tbl 14 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. 2. RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations. 3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table. 5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented during the two cycles. 6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
ADDRESS POINTER LOAD CONTROL (SLD)
In SLD mode, there is an internal delay of one cycle before the address pointer changes in the cycle following SLD. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer changes to the
SSTRT2
address location contained in the data-in register. SSTRT1, may not be low while SLD is LOW, or during the cycle following SLD. The SSTRT1 and SSTRT2 require only one clock cycle, since these addresses are pre-loaded in the registers already.
SLD
MODE (1)
SLD
(1)
SCLK A SI/O0-11 ADDRIN B C DATAOUT
SSTRT1,2
3099 drw 08
NOTE: 1. At SCLK edge (A), SI/O0-SI/O11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be high to ensure for proper sequential address pointer loading. At SCLK edge (B), SLD and SSTRT1,2 must be high to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER (1)
15 MSB H 14 H 13 H 12 L 11 -------------------------------------------------------------------------------------------------- 0 Address Loaded into Pointer LSB SI/O BITS
3099 drw 09
NOTE: 1. "H" = VIH and "L" = VIL for the SI/O intput state.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
Reset (RST RST) RST
Setting RST LOW resets the control state of the SARAM. RST functions asynchronously of SCLK (i.e. not registered). The default states after a reset operation are displayed in the adjacent chart.
EOB
Register Address Pointer Flags Buffer Flow Mode Start Address Buffer #1 End Address Buffer #1 Start Address Buffer #2 Registered State
(1)
Contents 0 Cleared to High state BUFFER CHAINING 0 4095 (1) (4K)
Cleared (set at invalid points) Cleared (set at invalid points)
SCE
End Address Buffer #2(1)
= VIH, SR/W = VIL
NOTE: 3099 tbl 15 1. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode" section.
BUFFER COMMAND MODE (CMD CMD) CMD
Buffer Command Mode (CMD) allows the random access port to control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0-I/O11 are used to access the start of buffer and the end of buffer addresses and to set the flow control mode of each buffer. The Buffer Command Mode also allows reading and clearing the status of the EOB flags. Seven different CMD cases are available depending on the conditions of A0-A2 and R/W. Address bits A3-A11 and data I/O bits I/O12-I/O15 are not used during this operation.
RANDOM ACCESS PORT CMD MODE(1)
Case # 1 2 3 4 5 6 7 8 A2-A0 000 001 010 011 100 101 101 110/111 R/W 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 1 (X) DESCRIPTIONS Write (read) the start address of Buffer #1 through I/O0-I/O11. Write (read) the end address of Buffer #1 through I/O0-I/O11. Write (read) the start address of Buffer #2 through I/O0-I/O11. Write (read) the end address of Buffer #2 through I/O0-I/O11. Write (read) flow control register Write only - clear EOB1 and/or EOB2 flag Read only - flag status register (Reserved)
3099 tbl 16
NOTE: 1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION (1,2)
15 MSB H 14 H 13 H 12 L 11 -------------------------------------------------------------------------------------------------- 0 Address Loaded into Buffer LSB I/O BITS
3099 drw 10
NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state. 2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and CE = VIH.
CASE 5: BUFFER FLOW MODES
Within the SARAM, the user can designate one of two buffer flow modes for each buffer. Each buffer flow mode defines a unique set of actions for the sequential port address pointer and EOB flags. In BUFFER CHAINING mode, after the address pointer reaches the end of the buffer, it sets the corresponding EOB flag and continues from the start address of the other buffer. In STOP mode, the address pointer stops incrementing after it reaches the end of the buffer. There is no linear or mask mode available.
6.30
9
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW CONTROL REGISTER DESCRIPTION(1,2)
15 MSB H H H H H H H H H H H 4 3 2 1 0 0 LSB I/O BITS
Counter Release (STOP Mode Only)
Buffer #1 flow control
3099 drw 11
Buffer #2 flow control
NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state. 2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
FLOW CONTROL BITS(5)
Flow Control Bits Bit 1 & Bit 0 (Bit 3 & Bit 2) 00 01 Mode Functional Description BUFFER CHAINING STOP
EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1).(1,3) EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The address pointer will stop incrementing when it reaches the next address ( EOB address + 1), if CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,2,4)
3099 tbl 17 NOTES: 1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value. 2. CMD Flow Control bits are unchanged, the count does not continue advancement. 3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1. 4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow control will remain in the stop mode. 5. Flow Control Bit settings of '10' and '11' are reserved. 6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode" section. RST conditions are not set to valid addresses.
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1)
15 MSB H H H H H H H H H H H H H H 1 0 0 LSB I/O BITS
NOTE: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
End of buffer flag for Buffer #1 End of buffer flag for Buffer #2
3099 drw 12
CASE 6: FLAG STATUS REGISTER WRITE CONDITIONS
Flag Status Bit 0, (Bit 1) 0 1 Functional Description Clears Buffer Flag EOB1, (EOB2). No change to the Buffer Flag.(2)
(1)
NOTES: 3099 tbl 18 1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone, or both may be cleared. 2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
Flag Status Bit 0, (Bit 1) Functional Description 0
EOB1 (EOB2) flag has not been set, the Pointer has not reached the End of the Buffer. EOB1 (EOB2) flag has been set, the Pointer has reached the End of the Buffer.
3099 tbl 19
1
6.30
10
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
IDT70824X20 Com'l. Only Symbol READ CYCLE tRC tAA tACE tBE tOE tOH tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Select Low-Z Time(1) Byte Enable Low-Z Time(1) Output Enable Low-Z Time(1)
(1)
IDT70824X25 Com'l. Only Min. 25 -- -- -- -- 3 3 3 2 -- -- -- 0 -- Max. -- 25 25 25 10 -- -- -- -- 12 12 11 -- 25
IDT70824X35 Min. 35 -- -- -- -- 3 3 3 2 -- -- -- 0 -- Max. -- 35 35 35 15 -- -- -- -- 15 15 15 -- 35
IDT70824X45 Min. 45 -- -- -- -- 3 3 3 2 -- -- -- 0 -- Max. -- 45 45 45 20 -- -- -- -- 15 15 15 -- 45 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Min. 20 -- -- -- -- 3 3 3 2 -- -- -- 0 --
Max. -- 20 20 20 10 -- -- -- -- 10 10 9 -- 20
Chip Select High-Z Time(1) Byte Enable High-Z Time Output Enable High-Z Time(1) Chip Select Power-Up Time Chip Select Power-Down Time
NOTES: 3099 tbl 20 1. Transition measured at 200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not production tested. 2. "X" in part number indicates power rating (S or L). 3. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
IDT70824X20 Com'l. Only Symbol WRITE CYCLE tWC tCW tAW tAS tWP tBP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write(3) Address Set-up Time Write Pulse Width(3) Byte Enable Pulse Width(3) Time(1) Write Recovery Time Write Enable Output High-Z Data Set-up Time Data Hold Time Output Active from End-of-Write 20 15 15 0 13 15 0 -- 13 0 3 -- -- -- -- -- -- -- 10 -- -- -- 25 20 20 0 20 20 0 -- 15 0 3 -- -- -- -- -- -- -- 12 -- -- -- 35 25 25 0 25 25 0 -- 20 0 3 -- -- -- -- -- -- -- 15 -- -- -- 45 30 30 0 30 30 0 -- 25 0 3 -- -- -- -- -- -- -- 15 -- -- -- ns ns ns ns ns ns ns ns ns ns ns
3099 tbl 21
IDT70824X25 Com'l. Only Min. Max.
IDT70824X35 Min. Max.
IDT70824X45 Min. Max. Unit
Parameter
Min.
Max.
NOTES: 1. Transition measured at 200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not production tested. 2. "X" in part number indicates power rating (S or L). 3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing. 4. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ). 6.30 11
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: READ CYCLES (1,2)
tRC ADDR tAA tACS
(2)
tOH
tCLZ , tBE tBLZ
tCHZ
tBHZ
tOE tOLZ I/OOUT Valid Data Out
tOHZ
3099 drw 13
NOTES: 1. R/W is HIGH for Read cycle. 2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
RANDOM ACCESS PORT WAVEFORM: READ CYCLE BUFFER COMMAND MODE
tRC ADDR tAA
(1)
tOH tACS
tCLZ , tBE tBLZ tOE tOLZ I/OOUT Valid Data Out
tCHZ
tBHZ
tOHZ
3099 drw 14
NOTE: 1. CE = VIH when
CMD = VIL.
6.30
12
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.1 (R/W CONTROLLED TIMING) (1,6) W
tWC ADDR tAW R/W tAS tWP
(5) (2) (3)
tWR
CE, LB, UB
I/OIN
(8)
tDW Valid Data In
tDH
OE
tOHZ tWHZ I/OOUT Data Out
(4) (4)
Data Out tOW
tACS tBE
3099 drw 15
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.2 (CE LB AND/OR UB CONTROLLED TIMING)(1,6,7) CE, CE LB,
tWC ADDR
(8) (5)
tAW tAS
CE, LB, UB
R/W
tCW (2) tBP (2) tDW tDH
tWR
(3)
I/OIN
Valid Data
3099 drw 16
NOTES: 1. R/W, CE, or LB and UB must be inactive during all address transitions. 2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL. 3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state and the input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing. 7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.30
13
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
IDT70824X20 Com'l. Only Symbol READ CYCLE tCYC tCH tCL tES tEH tSOE tOLZ tOHZ tCD tCKHZ tCKLZ tEB Sequential Clock Cycle Time Clock Pulse High Clock Pulse Low Count Enable and Address Pointer Set-up Time Count Enable and Address Pointer Hold Time Output Enable to Data Valid Output Enable Low-Z Time(1) Output Enable High-Z Time(1) Clock to Valid Data Clock High-Z Time(1) Clock Low-Z Time(1) Clock to EOB 25 10 10 5 2
--
IDT70824X25 Com'l. Only Min. 30 12 12 5 2 -- 2 -- -- -- 3 -- Max. -- -- -- -- -- 10 -- 11 25 14 -- 15
IDT70824X35 Min. 40 15 15 6 2 -- 2 -- -- -- 3 -- Max. -- -- -- -- -- 15 -- 15 35 17 -- 18
IDT70824X45 Min. 50 18 18 6 2 -- 2 -- -- -- 3 -- Max. -- -- -- -- -- 20 -- 15 45 20 -- 23 Unit ns ns ns ns ns ns ns ns ns ns ns ns
3099 tbl 22
Parameter
Min.
Max. -- -- -- -- -- 8 -- 9 20 12 -- 13
2 -- -- -- 3 --
NOTES: 1. Transition measured at 200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not production tested. 2. "X" in part numbers indicates power rating (S or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
IDT70824X20 Com'l. Only Symbol WRITE CYCLE tCYC tFS tWS tWH tDS tDH Sequential Clock Cycle Time Flow Restart Time Chip Select and Read/Write Set-up Time Chip Select and Read/Write Hold Time Input Data Set-up Time Input Data Hold Time 25 13 5 2 5 2 -- -- -- -- -- -- 30 15 5 2 5 2 -- -- -- -- -- -- 40 20 6 2 6 2 -- -- -- -- -- -- 50 20 6 2 6 2 -- -- -- -- -- -- ns ns ns ns ns ns
3099 tbl 23
IDT70824X25 Com'l. Only Min. Max.
IDT70824X35 Min. Max.
IDT70824X45 Min. Max. Unit
Parameter
Min.
Max.
NOTE: 1. "X" in part numbers indicates power rating (S or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
IDT70824X20 Com'l. Only Symbol RESET CYCLE tRSPW tWERS tRSRC tRSFV Reset Pulse Width Write Enable High to Reset High Reset High to Write Enable Low Reset High to Flag Valid 13 10 10 15 -- -- -- -- 15 10 10 20 -- -- -- -- 20 10 10 25 -- -- -- -- 20 10 10 25 -- -- -- -- ns ns ns ns
3099 tbl 24
IDT70824X25 Com'l. Only Min. Max.
IDT70824X35 Min. Max.
IDT70824X45 Min. Max. Unit
Parameter
Min.
Max.
NOTE: 1. "X" in part numbers indicates power rating (S or L).
6.30
14
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, NON-INCREMENTING READ
tCYC tCH SCLK tCL tES tEH
(3) (2)
CNTEN
tES tEH
(1)
SLD
tDS SI/OIN
tDH Dx tWS tWH SR/W tWS tWS tWH tWH tCD tCSZ tCKHZ A0 tWS tWH HIGH IMPEDANCE
SCE
SOE
SI/OOUT
tSOE tOLZ D0 tCKLZ D0 D0
3099 drw 17
tOHZ
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, BURST READ
tCH SCLK tCYC tCL tES
(3)
tEH
(2)
CNTEN
tES tEH
(1)
SLD
tDS SI/OIN Dx tWS tWH SR/W tWS A0
tDS tDH HIGH IMPEDANCE tWS
tDH
D2
tWH
SCE
SOE
SI/OOUT
tWH
tWS
tWH tCD tSOE tOLZ D0 tCKLZ D1 tOHZ
(2)
3099 drw 18
NOTES: 1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.30
15
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: READ STRT/EOB FLAG TIMING
tCH SCLK tCYC tCL tES
(4)
tEH
(2)
CNTEN
tES tEH
(1)
SSTRT1/2
SI/OIN Dx tWS tWH SR/W tWS
tDS HIGH IMPEDANCE tWS
tDH
D3
tWH
SCE
SOE
SI/OOUT
tWH
(3)
tWS tWH tCD tSOE tOLZ
(5)
tOHZ D0 tCKLZ tEB
3099 drw19
D1
D2
(2)
EOB1/2
NOTES: 1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. SOE will control the output and should be High on Power-Up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control the bus contention and permit a Write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT. 5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.30
16
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES
tCH SCLK tCYC tCL tES tEH tES tEH
(4)
CNTEN
tES tEH
(1)
(3)
SLD
tDS SI/OIN Dx tWS SR/W tWS tWH A0
tDH
tDS D0 tWS tWH
tDS tDH HIGH IMPEDANCE D1
tDH
(4)
SCE
SOE
SI/OOUT
tWH
tWS
tWH tCD
(5)
tCKHZ tOHZ HIGH IMPEDANCE
3099 drw 20
D0 tCKLZ
D0
SEQUENTIAL PORT WAVEFORM: BURST WRITE CYCLES
tCYC tCH SCLK tCL tES
(3)
tEH
(2)
CNTEN
tES tEH
(1)
SLD
tDS SI/OIN Dx tWS SR/W tWS tWH A0
tDS tDH D0 tWS tWH
tDH D1 D2
(5)
SCE
SOE
SI/OOUT
tWH
tWS
tWH
(5)
tCKLZ tCD
HIGH IMPEDANCE
D2
3099 drw 21
NOTES : 1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is Low. 4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.30
17
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES(STRT/EOB FLAG TIMING)
tCH tCL SCLK tES
(4)
tEH
(2)
CNTEN
tES tEH
(1)
SSTRT1/2
tDS tDH SI/OIN Dx tWS tWH SR/W tWS tWS tWH
(3)
D0
D1 tWS tWH
D2
D3
HIGH IMPEDANCE
(5)
SCE
SOE
SI/OOUT
tWH
(6)
tCKLZ tCD
HIGH IMPEDANCE
D3 tEB
3099 drw 22
EOB1/2
NOTES: 1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. SOE will control the output and should be High on Power-Up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control the bus contention and permit a Write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT. 5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.30
18
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, WRITE CYCLE(1, 4, 6)
SCLK
RST
CNTEN
(2)
SI/OIN
D0
D1
D2
D3
D4
3099 drw 23
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, READ CYCLE(1, 4)
SCLK
SR/
(3)
(5)
SI/OOUT
D0
(5)
D1
D2
D3
3099 drw 24
NOTES: 1. 'D0' represents data input for Address=0, 'D1' represents data input for Address=1, etc. 1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point. 3. Data output is available at a tCD after the SR/W=VIH is clocked. The RST sets SR/W=Low internally and therefore disables the output until the next clock. 4. SCE=VIL throughout all cycles. 5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point. 6. SR/W=VIL.
6.30
19
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: RESET TIMING
tRSPW
tRSRC R/ ( SR/ or (4) +)
tWERS tRSFV
1/2
Flag Valid
3099 drw 25
RANDOM ACCESS PORT WAVEFORM: RESTART TIMING OF SEQUENTIAL PORT (1)
0.5 x tCYC tFS SCLK
R/
(2)
2-5ns 6-7ns
CLR (3) Block (Internal Signal)
3099 drw 26
NOTES: 1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5). 2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5). 3. CLR is an internal signal only and is shown for reference only. 4. Sequential port must also prohibit SR/W or SCE from being low for tWERS and tRSRC periods, or SCLK must not toggle from Low-to-High until after tRSRC.
6.30
20
IDT70824S/L HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B G PF 20 25 35 45 S L 70824 Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 84-pin PGA (G84-3) 80-pin TQFP (PN80-1) Commercial Only Commercial Only
Speed in nanoseconds
Standard Power Low Power 64K (4K x 16) Sequential Access Random Access Memory
3099 drw 27
6.30
21

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